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Lead RTL design Engineer

AMD· Engineering
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BangaloreFull-timePosted 2mo ago

About the role

Lead RTL design engineer responsible for SoC design, integration, and verification across AMD’s IPs and full-chip implementation, with leadership in one design domain and collaboration with verification and physical design teams.

Responsibilities

  • SoC-level design and integration
  • Integration of IPs, SoC fabric, voltage crossings, clock crossings, resets, fuses, and I/O
  • RTL design and coding for SoC logic and features
  • SoC power design and power implementation activities
  • Static verification including: RTL Lint, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), Power checks, Connectivity checks
  • Debugging simulation and integration issues spanning multiple IPs in collaboration with verification teams
  • Supporting top-level synthesis and collaborating with physical design teams for full-chip implementation
  • Leading one of the design domains (integration, power, CDC/RDC, connectivity, etc.)

Qualifications

  • 8+ years of SoC Design and Verilog RTL development experience
  • BE/B.Tech/ME/M.Tech (ECE/EEE or equivalent)

Skills

Required:Verilog RTL developmentSoC integrationSystem interconnect protocols (AXI, PCIe)Scripting (Tcl, Perl, Ruby, Shell)Communication
Nice to have:UPF and low-power methodologiesStatic timing analysis (STA)Formal verification techniques/tools

Benefits

  • Benefits offered are described in AMD benefits at a glance (link provided)
Last updated Oct 22, 2026. Interested? Apply on the company site.
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