Silicon Verification Engineer
Hybrid (Singapore)Full-timePosted 2mo ago
About the role
Verification Engineer to join the DDR PHY IP development team, focusing on verifying high-performance DDR PHY IP used in cutting-edge SoCs across data center, mobile, and automotive markets. Entry-level role emphasizing development of robust verification environments, design correctness, and silicon quality.
Responsibilities
- Develop and maintain UVM-based verification environments for DDR PHY IP.
- Write and execute test plans, directed and constrained-random tests, and functional coverage models.
- Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.
- Create and maintain verification collateral, including testbenches, checkers, and scoreboards.
- Perform regression runs, track functional coverage, and ensure full design verification closure.
- Contribute to automation scripts for regression, data analysis, and verification efficiency improvements.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Strong understanding of digital design fundamentals (clocking, timing, state machines, analog design basics).
- Experience with SystemVerilog and UVM (academic or internship exposure preferred).
- Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
- Basic understanding of DDR memory protocols and PHY architecture is a plus.
- Proficiency in scripting languages (Python, Perl, or TCL) for automation.
- Excellent analytical, debugging, and communication skills.
- Enthusiasm for learning and problem-solving in a collaborative, fast-paced environment.
Skills
Required:UVM-based verificationSystemVerilogTest planning and coverageDebuggingScripting for automation
Nice to have:DDR PHY/IP verification
Benefits
- Benefits offered are described in AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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