DFT- SCAN/ATPG
BangaloreFull-timePosted 2mo ago
About the role
DFx engineer to join AMD’s CDFX team, contributing to DFx methodologies and advanced design practices for the next generation of AMD silicon (SCAN, ATPG, MBIST, BSCAN, etc.). Collaborative role across RTL, verification, and PD teams to implement and accelerate DFX design and verification in complex SoC/ASIC designs.
Responsibilities
- Own/lead the DFX Design Architect, Develop and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc.
- Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design
- Design and develop correct by construction DFX design and support DFX verification
- Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects.
- Work with the Synthesis and PD team to ensure correct DFT implementation in Scan/ATPG.
Qualifications
- Experience and understanding of ASIC DFX, Scan synthesis, Integration flow using Fusion Compiler, ATPG experience in tile and SoC level experience
- Familiar with scan hardware compressions, failure mechanisms and debug processes
- Familiar in ICl Extraction, SSN, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC
- Experience in End-to-End DFX flow development/creation
- DC/AC scan (at-speed) development, debug, and test
- Expert in at least one scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts for DFX implementation
- Strong EDA tools experience: Tessent (Testkompress, SSN, IJTAG), Synopsys Fusion Compiler, Design Compiler, Spyglass
- Experience with RTL quality check tools/methodologies (Spyglass, Lint)
- Exposure to Static timing analysis & Timing closure
- Scan/ATPG patterns & test flows development, debug, test, and characterization
- Excellent hands-on debugging and scripting skills
- Strong problem-solving skills; knowledge of low power concepts (clock gating, power gating) is a plus
- Academic credentials: Bachelors or Masters in Computer/Electrical Engineering (SoC integration)
Skills
Required:DFX design and implementationScan synthesisATPGScripting (Perl, Python, TCL)EDA tools (Tessent, Spyglass, etc.)Debug skills
Nice to have:Fusion CompilerStatic timing analysis / Timing closure
Benefits
- AMD benefits at a glance (link provided in job description)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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