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Design Verification Engineer

AMD· Engineering
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Hybrid (Markham, ON)CA$91.2k - CA$136.8kFull-timePosted 2mo ago

About the role

Design Verification Engineer on the Data Accelerator (DACC) team at AMD, focusing on IP verification for next-generation hardware accelerators, with emphasis on automation, PPV, and emulation support in a fast-growing verification environment.

Responsibilities

  • Develop and maintain block level IP verification testbenches, test methodology and infrastructure, with guidance from senior team members
  • Develop detailed test plans for covering new features, under the direction of a lead or senior engineer
  • Triage regressions, debug simulations, and analyze coverage; escalate and collaborate with design, verification and other teams to help achieve verification closure
  • Deploy industry leading verification methodologies such as UVM, formal verification etc.
  • Take ownership of assigned features within a block, with support from senior engineers on end-to-end planning
  • Reproduce silicon functional bugs in simulations and/or formal verification tools
  • Conduct and participate in code reviews

Qualifications

  • Hands-on hardware verification experience (at-least one tapeout, internship or co-op)
  • Proficient in Verilog, SystemVerilog, UVM and working in Linux and Windows environments
  • Curiosity about applying AI agents and skills to functional verification tasks
  • Excellent programming skills
  • Familiarity with Makefiles, scripting languages like perl, python, ruby etc.

Skills

Required:VerilogSystemVerilogUVMLinux
Nice to have:WindowsMakefilesPythonPerl/RubyAI in verification
Last updated Oct 22, 2026. Interested? Apply on the company site.
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