Leadership Role - DFT
Hybrid (Bangalore, India)Full-timePosted 2mo ago
About the role
Principal Member of Technical Staff (PMTS) in the IODC SoC DFT organization leading end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs powering next-generation SOCs; responsible for DFT architecture definition through production test enablement, silicon bring-up, and manufacturing ramp with cross-functional collaboration.
Responsibilities
- Own end-to-end ATPG execution for large-scale SoCs from architecture phase through silicon production.
- Define and drive ATPG methodologies, test strategies, coverage closure plans, and pattern signoff criteria.
- Generate and validate scan, transition fault, cell-aware, bridge, chain diagnosis, and compression-based ATPG patterns.
- Drive pattern quality improvements, tester efficiency optimization, and test cost reduction initiatives.
- Partner closely with DFT RTL, DFT Verification, RTL, Physical Design, and Timing teams to ensure robust DFT implementation and testability.
- Collaborate with PEO and ATE teams to enable tester bring-up, pattern correlation, tester debug, and manufacturing deployment.
- Lead pattern validation activities across simulation, emulation, ATE, and platform environments.
- Drive root-cause analysis and resolution of ATPG, tester, silicon, and yield-related issues.
- Ensure high-quality pattern delivery meeting schedule, coverage, power, and manufacturing requirements.
- Support silicon bring-up, diagnosis, yield learning, and production ramp activities.
- Develop automation flows and AI-enabled solutions to improve ATPG productivity and debug turnaround time.
- Mentor junior engineers and drive ATPG best practices across the organization.
Qualifications
- 16+ years of experience in SoC DFT with strong expertise in ATPG and manufacturing test.
- Proven ownership of ATPG execution for multiple successful high-volume SoC products.
- Extensive experience with multi-million gate SoCs and hierarchical ATPG methodologies.
- Deep understanding of Scan, EDT/Compression, LBIST, MBIST, Boundary Scan, and DFT architecture.
- Strong experience with pattern validation, tester correlation, and post-silicon debug.
- Hands-on experience working with Product Engineering, Test Engineering, and ATE teams.
- Experience debugging silicon failures and supporting yield improvement initiatives.
- Strong scripting and automation skills using Python, Perl, Tcl, Shell, or similar languages.
- Demonstrated ability to lead technical initiatives across geographically distributed teams.
Skills
Required:ATPGScan architectures and compressionPattern validationAutomation and scriptingDebug and root-cause analysisCross-functional leadership
Benefits
- Benefits offered are described: AMD benefits at a glance
Last updated Oct 1, 2026. Interested? Apply on the company site.
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