IP/Subsystem Verification Lead
HyderabadFull-timePosted 2mo ago
About the role
Principal Design Verification Engineer leading verification efforts for RTL blocks, subsystems, and SOCs for AMD’s Data Center Networking ASICs within the Network Technology Solutions Group (NTSG).
Responsibilities
- Lead the verification efforts to functionally verify complex RTL blocks and SOCs destined for the next generation of Data Center networking ASICs
- Experience of working as a technical lead in a verification team
- Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems.
- Strong experience in UVM-based verification in SystemVerilog, with a deep understanding of the framework.
- Experience of verification coverage closure in an ASIC or FPGA project.
- Strong problem-solving skills.
- Experience of Synopsys functional verification tools would be an advantage.
- Experience of full chip verification would be an advantage.
- Experience of formal verification would be an advantage.
- Knowledge of AI-based debug techniques would be an advantage.
- Knowledge of Python would be an advantage.
- Experience in C/C++ would be an advantage.
- RTL design experience would be an advantage.
- Experience in networking technologies and products would be an advantage.
Qualifications
- Bachelor’s or Master’s degree in related discipline preferred
Skills
Required:Verification lead experienceSimulation-based verificationUVM-based verificationVerification coverage
Nice to have:Synopsys toolsFormal verificationPythonC/C++RTL designNetworking technologies
Benefits
- AMD benefits at a glance (as described in linked page)
Last updated Oct 22, 2026. Interested? Apply on the company site.
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