Digital Design Verification Engineer
Hybrid (Markham, Ontario; Vancouver, Canada)CA$128k - CA$192kFull-timePosted 2mo ago
About the role
Verification engineer role within the PCIe Subsystem team focused on SystemVerilog/UVM-based testbenches and memory sub-system verification for PCIe features, with collaboration across multiple sites/time zones in AMD.
Responsibilities
- Develop and enhance System Verilog/UVM-based testbenches for verifying new and existing PCIe features.
- Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in memory sub-system architecture.
- Create staging and test plans for new feature development.
- Effectively testing a design by understanding the functional and performance goals.
- Take ownership of different verification tasks.
- Improve productivity through automation using AI tools
Qualifications
- Bachelor’s or Master’s degree in related discipline preferred.
Skills
Required:SystemVerilogUVMPCIe verification
Nice to have:memory sub-system architecturedebug tools (VCS, Debussy, DVE, Verdi)
Benefits
- AMD benefits at a glance (as described in the posting)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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