PD Architect
BangaloreFull-timePosted 2mo ago
About the role
Lead Physical Design Architect for RTL2GDSII flow, responsible for physical design implementation, timing closure, power optimization, and signoff strategies across multiple SOCs/ASICs, with mentorship and cross-functional leadership to achieve first-pass silicon success in AMD’s S3 India team.
Responsibilities
- Go to person for multiple SOC/ASICs in RTL2GDSII domain comprising of physical design implementation, timing closure and various signoff (timing, physical verification, IREM, Power etc) activities
- Provide leadership and mentoring towards convergence of highly complex tiles/partitions/blocks spanning across multiple Subsystems and IPs (e.g. PCIE, DDR, CPUs, GPUs, Gfx, ETH, UCIE)
- Cross-Functional Leadership - Collaborate with architecture, design, verification, DFT and product management to ensure PPA goals are met
- Strategic Planning: Provide strategic direction to SOC/Subsystem and Tile/Partition level execution
- Foster a culture of innovation by encouraging RTL2GDSII research, identifying opportunities for patents/publications
- Understand horizontal sign-off flows (VCLP, Formal Equivalence, Low Power Checks) with expert timing convergence knowledge for tile-level and full-chip timing
- Track project convergence status across design cycle milestones
- Drive methodology development and adoption of new flows/methodologies and AI technologies
- Collaborate with CAD and EDA vendors to strengthen closure methodology
- Provide technical direction, mentoring and support to the engineering team
- Stay updated on RTL2GDSII advancements and represent AMD in industry forums
- Define and track KPIs related to RTL2GDSII and report progress to leadership
- Collaborate with foundry DRM and cooperate with DTCO and FTO as needed
Qualifications
- B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering
- Ability to drive/manage projects from RTL to GDS with 5-10+ tape-outs experience
- Proficient in physical design EDA tools: Fusion Compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools
- Hands-on experience with Perl/TCL/Shell/Python scripting, Verilog/VHDL RTL design, and AI technologies
- Expert level understanding of EDA tools across Synopsys and Cadence
- Excellent presentation and communication skills
Skills
Required:Physical DesignSynthesis & Place & RouteRTL2GDSIIPower, Performance and Area (PPA) OptimizationEDA Tools (Synopsys/Cadence)Scripting
Benefits
- Benefits offered are described: AMD benefits at a glance (link provided)
Last updated Oct 22, 2026. Interested? Apply on the company site.
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