SoC DFX Scan / ATPG Engineer
Hybrid (Markham and Ottawa)CA$128k - CA$192kFull-timePosted 2mo ago
About the role
Role in AMD's SoC Design-for-Test (DFT) team responsible for implementing, verifying, optimizing, and deploying advanced DFT solutions including scan insertion and ATPG for complex SoCs. Collaborates with multiple engineering disciplines to improve test quality, manufacturability, and silicon bring-up.
Responsibilities
- Drive end-to-end SoC-level scan insertion, DFT implementation, and ATPG execution.
- Develop and optimize scan architectures, scan chains, test compression, and ATPG strategies.
- Analyze scan coverage and ATPG results to improve test quality and coverage.
- Support ATPG retargeting and hierarchical test integration methodologies.
- Debug scan, ATPG, simulation, and emulation issues from block level through full-chip integration.
- Develop and validate methodologies for stuck-at, transition, at-speed, and diagnostic pattern generation.
- Collaborate with design, verification, physical design, CAD, and product engineering teams to resolve DFT-related challenges.
- Support silicon bring-up, manufacturing test development, yield improvement, and failure analysis activities.
- Contribute to DFT planning and implementation of technologies such as scan compression, MBIST, LBIST, PLL-based at-speed testing, and on-chip debug infrastructure.
- Develop automation and scripting solutions to improve DFT productivity, quality, and scalability.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience with scan insertion, ATPG, and DFT methodologies.
- Strong knowledge of digital design fundamentals and ASIC development flows.
- Experience with test compression technologies and hierarchical ATPG flows.
- Experience debugging gate-level simulation, ATPG validation, and SoC integration issues.
- Familiarity with Verilog/SystemVerilog and digital logic design.
- Experience with scripting languages such as Python, Perl, Tcl, or Shell.
- Experience with SoC-level ATPG retargeting methodologies.
- Familiarity with emulation-based DFT validation and debug.
- Experience with silicon bring-up, diagnosis, and yield analysis.
- Knowledge of MBIST, LBIST, JTAG/IJTAG, Streaming Scan Network (SSN), or other advanced DFT methodologies.
- Experience supporting large-scale GPU, CPU, AI accelerator, or complex ASIC development.
Skills
Required:Scan insertionATPGDigital design fundamentals
Nice to have:MBIST/LBISTVerilog/SystemVerilogScripting (Python, Perl, Tcl, Shell)
Benefits
- AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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