Design Verification Engineer
Santa Clara, CA$136kFull-timePosted 2mo ago
About the role
Role focused on adaptive, self-motivated design verification for complex processor architectures, ASIC/SoC verification, collaborating with RTL, firmware, circuit, and architecture teams to deliver high-quality IP.
Responsibilities
- Develop/Maintain tests for functional verification.
- Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues.
- Work on functional & code coverage verification.
- Provide technical support to other teams
Qualifications
- Bachelors or Master’s or Ph.D. degree in computer engineering/Electrical Engineering
- Experience with Verilog, System Verilog and modern verification libraries like UVM
- Experience with C/C++
- Strong ASIC design verification experience
- Experience / Background with DDR or Memory Controller. PHY Verification is a plus
- Experience with scripting languages like Python, Perl and TCL is a plus
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Proficient in debugging RTL code using simulation tools
Skills
Required:VerilogSystemVerilogUVMC/C++
Nice to have:Memory controller / DDRScripting languages
Last updated Oct 15, 2026. Interested? Apply on the company site.
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