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CAD Engineer – PDV

Apple· Silicon Technologies
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Hybrid (Herzliya / Tel Aviv)Full-timePosted 2mo ago

About the role

CAD Engineer responsible for architecting, developing, maintaining and improving physical design verification (PDV) flows, collaborating with design, PD and integration teams to enable chip design and tapeout across various technology nodes and toolsets.

Responsibilities

  • Develop, improve and maintain all aspects of physical verification flow and methodology
  • Coordinate the effort of validating flows, improving for custom checks and data generation
  • Work with the design and PD teams to facilitate the chip design process
  • Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
  • Collaborate with tool vendors and foundries for PDK performance enhancements

Qualifications

  • Education: Minimum requirement of BS + 8 years of relevant industry experience
  • Requires experience in Silicon chip design flows, including place-and-route (PnR) implementation flows
  • Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL is required. Rule coding in PERC is a plus
  • Tapeout support and SoC chip-level PDV debug experience in various technology nodes is desirable
  • Hands-on experience with PnR tools and physical implementation flow is preferred
  • Knowledge/scripting in programming languages such as Perl, Python, Tcl, Shell, Makefile and/or C++
  • Deep understanding of Silicon technology and experience with flow development in advanced nodes
  • Knowledge of parasitic extraction and Virtuoso SKILL coding is a plus

Skills

Required:PDV flow developmentDRC/LVS/ERC/MFILL rule codingPnR flowsProgramming/Scripting
Last updated Aug 7, 2026. Interested? Apply on the company site.

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