Performance Engineer, Kernels
Bengaluru, ChennaiFull-timePosted 2mo ago
About the role
Senior performance engineering role focusing on kernel-level optimization for ML workloads, authoring custom CUDA/DSL/PTX kernels to close performance gaps in the kernel layer and improve production p99 metrics.
Responsibilities
- Own the kernel layer and author custom CUDA, DSL-based, and PTX kernels to close performance gaps when stock libraries underperform.
- Deliver kernels that beat published baselines on real workloads and drive measurable production performance improvements (p99).
- Explain the root causes of performance changes and how your code affects system metrics.
- Collaborate at the intersection of serving runtime, kernel layer, and SRE to maintain fleet reliability and performance.
Qualifications
- 5+ years in ML systems, with 2+ years authoring production CUDA kernels.
- Kernel in production that beat prior baseline by a measurable margin.
- CUDA at kernel-authoring level: thread-block sizing, shared-memory layout, warp primitives, async copies (cp.async, TMA), and MMA selection.
- CUTLASS / CuTe DSL at modify-and-extend level, comfort with layout algebra.
- PTX at debug-and-modify level, including hand-written PTX when needed.
- Nsight Compute and Systems fluency: ability to read a roofline plot and propose fixes.
- Attention kernels: authored or modified at least one (FlashAttention-family, paged, MLA, sliding-window, or sparse).
- Multi-architecture awareness: knowledge of changes from Hopper to Blackwell (TMA, WGMMA, tcgen05).
Skills
Required:Kernel authoring (CUDA)CUTLASS / CuTe DSLPTXNsight ComputeAttention kernels (FlashAttention, etc.)Multi-architecture awareness
Benefits
- Not specified in description but typically part of role (not included to avoid filler).
Last updated Aug 11, 2026. Interested? Apply on the company site.
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