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IP Verification Engineer

AMD· Engineering
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San Jose, CA$166.4kFull-timePosted 2mo ago

About the role

Senior ASIC Verification Engineer role focused on verifying PCIe/CXL-based IPs for FPGA/ASIC products in AMD's front-end design/integration team, collaborating across architecture, IP design, PD, and product engineering to achieve first-pass silicon success.

Responsibilities

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
  • Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
  • Build the directed and random verification tests
  • Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

Qualifications

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Skills

Required:PCIe/CXL/NVMe/Ethernet protocolsVerilog/System VerilogUVM based verification frameworksTestbench development
Nice to have:Scripting (Python/Perl)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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