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ASIC Design Verification Engineer

AMD· Engineering
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Rochester, NY$144.8k - $217.2kFull-timePosted 2mo ago

About the role

Role focused on verification strategy and coverage for mixed-signal power management IP, driving system-level verification of the full SoC, block-level verification, and RTL design within AMD.

Responsibilities

  • Own the overall verification strategy, test plan, and coverage closure for a mixed-signal power management IC
  • Define functional and code coverage goals, track progress, and report verification status and readiness to the project team
  • Own verification signoff criteria and drive the team to coverage closure ahead of tape-out
  • Maintain and improve regression infrastructure, triage flow, and results reporting
  • Develop and execute system-level verification of the full SOC, including boot and reset sequencing, power state transitions, fault and protection scenarios, and host interface traffic
  • Verify firmware-driven behavior in co-simulation of embedded firmware with RTL
  • Build and maintain SystemVerilog/UVM testbench components, sequences, checkers, and assertions at the system level
  • Develop block-level test benches and coverage for digital blocks as project needs require
  • Verify digital/analog interfaces using real-number models (RNM) of analog macros, including model bring-up, correlation to analog behavior, and debug in the digital simulation environment
  • Partner with Analog Design and RTL Design to review model fidelity and ensure the verified behavior matches silicon intent
  • Partner with RTL designers on design reviews, verification planning, and debug of failures to root cause
  • Contribute to SystemVerilog RTL design work across the team as needed
  • Support post-silicon bring-up, including correlation of silicon behavior back to pre-silicon test cases
  • Work across Analog, Firmware, Systems Engineering, and Architecture teams; mentor junior engineers on verification methodology

Qualifications

  • Bachelors or master's in electrical/computer engineering
  • System-level or SOC-level verification ownership on a mixed-signal device
  • Real-number modeling (RNM) of analog blocks in SystemVerilog (wreal / nettype real), or Verilog-AMS experience
  • SystemVerilog RTL design experience in an ASIC environment
  • Firmware/RTL co-simulation or hardware/software co-verification experience
  • Formal verification, assertion-based verification (SVA), or emulation/FPGA prototyping experience
  • Post-silicon bring-up and debug experience
  • Experience mentoring engineers and leading verification reviews
  • Strong SystemVerilog and UVM testbench development skills, ownership of verification for a block or subsystem through tape-out
  • Demonstrated experience defining verification plans and driving functional and code coverage to closure
  • Proficiency with simulation, coverage, and debug tools, and regression automation
  • Ability to read and understand RTL and design specifications to independently derive test intent

Skills

Required:verification planningSystemVerilog/UVM
Nice to have:RNM/Verilog-AMS

Benefits

  • Benefits offered are described in AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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