Senior SoC Design Verification Engineer
HyderabadFull-timePosted 2mo ago
About the role
Senior Silicon Design Verification Engineer responsible for leading verification of complex SoC features and subsystems, driving verification methodology, ensuring high-quality silicon sign-off, and mentoring engineers across the verification organization.
Responsibilities
- Own end-to-end verification of key SoC features and system-level scenarios.
- Develop and execute comprehensive verification plans, testbenches, and regression strategies.
- Drive functional, code, assertion, and scenario coverage closure.
- Lead SoC/IP integration verification and sign-off activities.
- Debug complex RTL, architecture, testbench, and firmware issues.
- Collaborate closely with Architecture, RTL, Firmware, Emulation, Platform, and Validation teams.
- Drive verification methodology improvements, automation, and productivity enhancements.
- Support pre-silicon bring-up, emulation, and post-silicon debug activities.
- Mentor and technically guide MTS/SDE engineers.
- Drive execution toward program milestones such as LSB, LSC, LSD, and Tape-Out
Qualifications
- Minimum 12+ years of experience in ASIC Design Verification
- Experiance in X86 based SOC DV
- Strong expertise in SoC verification methodologies.
- Advanced SystemVerilog and UVM knowledge.
- Experience with SoC/IP verification environments, VIPs, UVCs, BFMs.
- Strong debugging skills using industry-standard simulation and verification tools.
- Knowledge of functional and code coverage methodologies.
- Understanding of SoC architecture, interconnects, memory subsystems, security, power management, and performance features.
- Familiarity with scripting (Python/Perl/Shell), regression automation, and version control systems.
Skills
Required:SystemVerilogUVMSoC verificationDebugging
Nice to have:Python/Perl/Shell
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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