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Lead STA / Timing analysis Design Engineer

AMD· Engineering
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Hybrid (Bangalore)Full-timePosted 2mo ago

About the role

MTS Silicon Design Engineer (STA/Timing) at AMD, focused on development and signoff of timing constraints for IPs, blocks, subsystems, or full-chip, with strong SDC, Tcl, and EDA tool expertise, in a high-frequency digital design environment.

Responsibilities

  • Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
  • Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA
  • Well versed with timing signoff methodology and corner definitions
  • Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
  • Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
  • Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
  • Ensuring full chip level Interface timing closure along DRV closure
  • Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure

Qualifications

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Skills

Required:Timing constraint development (SDC)SDC analysis and signoffTcl scripting
Nice to have:EDA tools (Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker)DFT timing awarenessPhysical design flow understanding

Benefits

  • AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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