Design Verification Engineer
Hybrid (Santa Clara, CA), Hybrid (Folsom, CA; Austin, TX)$166.4kFull-timePosted 2mo ago
About the role
Verification Engineer role focusing on DDR interfaces and memory systems (DDR5, LPDDR5/LPDDR6, DFI) for AMD server products, requires SystemVerilog/UVM, C/C++, and scripting skills, with cross-functional collaboration and post-Si support.
Responsibilities
- Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
- Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
- Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
- Knowledge sharing and other contributions to verification methodology
- Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
Qualifications
- Bachelor’s +8years or Master’s degree +6 years in related discipline preferred
Skills
Required:SystemVerilogUVM (Universal Verification Methodology)C/C++Python/PerlRTL and micro-architecture understandingMemory interface knowledge (DDR5, LPDDR5, DFI)
Nice to have:SystemVerilog assertions/constraints/coverage
Last updated Oct 22, 2026. Interested? Apply on the company site.
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