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Design Verification Engineer

AMD· Engineering
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Hybrid (Santa Clara, CA)$153k - $229.4kFull-timePosted 2mo ago

About the role

Experienced Verification Engineer to drive verification efforts for DDR interfaces and memory systems in AMD's server products, with emphasis on SystemVerilog/UVM, C/C++, and scripting, across DDR5/LPDDR5/DFI and related DIMMs.

Responsibilities

  • Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
  • Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
  • Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
  • Knowledge sharing and other contributions to verification methodology
  • Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

Qualifications

  • Bachelor’s +8years or Master’s degree +6 years in related discipline preferred

Skills

Required:SystemVerilogUVM (Universal Verification Methodology)C/C++Python/Perl scripting
Nice to have:Memory interface architectures

Benefits

  • Benefits offered are described: AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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