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CPU Gate Level Synthesis Engineer

Apple· Hardware
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Santa Clara, CA$129.3k - $194.7kFull-timePosted 2mo ago

About the role

CPU Gate Level Synthesis role within Apple’s Silicon Engineering Group (SEG) focused on early-stage development of high-performance, low-power digital designs for CPUs. Responsibilities include RTL to gate-level synthesis, timing/power/area optimization, and collaboration across RTL, physical design, DFT, and timing teams to ensure high fidelity synthesis feedback and efficient, scalable designs.

Responsibilities

  • Early RTL health assessment to detect potential timing/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions
  • Early stage power estimation and validation for new micro-architectural features
  • Enhancing synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback
  • Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow
  • Partner with timing team to enable constraints generation at top levels
  • Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs
  • Track and analyze PPA trends through project cycle

Qualifications

  • Minimum BS required
  • Experience in at least one of the following: digital logic design, RTL synthesis, physical design

Skills

Required:RTL synthesisdigital logic design
Nice to have:physical designDFT/ATPG/MBISTscripting (TCL/Perl/Python)

Benefits

  • Comprehensive medical and dental coverage
  • retirement benefits
  • range of discounted products and free services
  • reimbursement for certain educational expenses including tuition
  • discretionary bonuses or commission payments (may apply)
  • relocation (may apply)
  • employee stock programs including RSUs and Employee Stock Purchase Plan (ESPP)
Last updated Aug 21, 2026. Interested? Apply on the company site.

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