Circuit Design Engineer - Library/Process Monitor
Apple· Hardware
Beaverton, ORfull-timePosted 2mo ago
About the role
Be at the heart of processor design in deep submicron technologies, focusing on standard cell library design and circuit-level optimization. Drive library architecture, PPA improvements, and process monitor IP development, collaborating across CPU, SOC, and GPU teams to deliver ready-to-market products.
Responsibilities
- Work on library architecture discussion & optimization effort to improve overall Library PPA.
- Drive layout optimization effort by identifying & reducing parasitics to push circuit PPA.
- Work on Library PPA for different technology, architecture, PDK releases.
- Develop standard cell circuits that push design PPA.
- Work on PNR block to design process monitor IP, validate other IPs in testchips.
- Engage with CPU, SOC and GPU teams on physical design requirements.
Qualifications
- Bachelor's Degree + minimum of 3 years of experience
- Experience in Circuit design of high-performance flip flops, level shifters, retention flops and other complex circuits is a plus
- Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus
Skills
Required:Circuit design
Nice to have:RTL2GDSII flowStatic Timing Analysis (STA)Library architecture
Last updated Sep 25, 2026. Interested? Apply on the company site.
About Apple
Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.
Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.
AirPods Max 2Apple ArcadeApple CardApple Fitness+Apple MusicApple TVApple TV+Apple Watch Series 11
More open roles at Apple
- Senior UI Software Engineer, Cocoa2d agoCupertino, CA · Software and Services
- AIML - Machine Learning Engineer, Visual Intelligence Technology2d agoHybrid (Cupertino/Santa Clara/SSeattle area (3 work locations)) · Visual Intelligence Technology
- Physical Design Methodology CAD Engineer2d agoHybrid (Sunnyvale, California), Hybrid (Austin, Texas) +3 more · Hardware Technology CAD team / Silicon Technologies group
- Sr. ML Optimization Engineer, ASE Efficiency2d agoHybrid (San Diego, CA) · Software and Services
- Sr. ML Optimization Engineer, ASE Efficiency2d agoHybrid (Seattle, WA) · Software and Services