RTL Design & Integration Engineer
San Jose, CA$166.4k - $249.6kFull-timePosted 2mo ago
About the role
Role within AMD's FPGA Product development team focusing on RTL design, IP integration, and AI-driven automation to optimize silicon implementation and development timelines for Adaptive & Embedded Computing Group (AECG) device programs.
Responsibilities
- Collaborate with architects, hardware engineers, and SW-FW engineers to understand product requirements and IP features.
- Build early-stage RTL designs based on product and architecture intent driving Silicon and Solution co-development.
- Build and enhance AI-driven infrastructure to accelerate IP integration and improve development timelines.
- Apply data-driven methodologies to align engineering teams across next-generation products and technology nodes.
- Support functional simulation and software quality checks, ensuring robust verification coverage.
- Partner with global teams to achieve seamless integration and delivery.
Qualifications
- Bachelor’s or Master’s in Computer Engineering or Electrical Engineering
- Targeting background expertise in RTL design (Verilog/SystemVerilog), including digital/analog block implementation
- Understanding of VLSI design flow, from RTL through Physical Design and GDSII
- Familiarity with Physical Implementation processes: floorplanning, synthesis, P&R, STA
- Experience with EDA tools (Synopsys Design Compiler, Primetime, VCS; Cadence Virtuoso)
- Knowledge of UVM/OVM verification, simulation environments, and debugging
- Understanding of FPGA architecture and usage models is a plus
- Proficiency in scripting (Perl, Tcl, Python, Shell) for design automation
- Excellent communication skills and ability to thrive in a fast-paced, global environment
Skills
Required:RTL designVLSI design flowPhysical ImplementationEDA toolsScripting
Nice to have:VerificationFPGA architecture
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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