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Fullchip Floorplan Physical Design Engineer

AMD· Engineering
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Hybrid (Markham, ON)CA$155.2k - CA$232.8kFull-timePosted 1mo ago

About the role

Physical Design engineer responsible for full-chip floorplanning, physical implementation, timing closure, and power optimization for complex SoC designs at AMD, located in Markham, ON, Canada.

Responsibilities

  • Define chip-level partitioning, block placement strategy, and macro integration to meet design and performance goals
  • Demonstrate hands-on expertise in full-chip floorplanning, including feedthrough topology planning, repeater insertion, top-level port/pin assignment and alignment, and source-synchronous bus layout
  • Optimize full-chip floorplan for timing, power, and area across the entire chip
  • Collaborate closely with RTL, physical design, and architecture teams to gather and implement design requirements effectively
  • Conduct layout feasibility studies through what-if analysis and trade-off evaluations
  • Utilize industry-standard EDA tools such as Cadence Innovus, Synopsys ICC, and Calibre for physical implementation and verification
  • Develop and maintain automation scripts using Tcl, Perl, and Python to enhance floorplanning efficiency and consistency
  • Apply low-power design techniques; familiarity with voltage domain crossing checks is a strong asset

Qualifications

  • Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering

Skills

Required:Full-chip floorplanningSynthesis, place and routeTiming closurePower optimizationScripting
Nice to have:Verilog RTL design

Benefits

  • AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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