SDC, Synthesis and STA Engineer
Hybrid (Bangalore)Full-timePosted 1mo ago
About the role
Role focused on front end implementation of IPs and its closure, including SDC development/generation, verification, promotion/demotion, equivalence checking, with potential expansion to synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure; collaboration with design and PNR teams; guidance to team members.
Responsibilities
- Own constraints, SDC development for IPs, SS and SoCs, including SDC generation, verification, promotion, demotion and equivalence using third party or self-built tools
- Front end implementation responsibilities may include synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
- Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
- Collaborate with designer and PNR teams to achieve closure
- Understand duration required, plan and execute as per schedule
- Complete quality delivery for synthesis and timing closure
- Debug and resolve technical issues
Qualifications
- Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering
Skills
Required:SDC development and constraintsDebugging
Nice to have:Synthesis, LEC, CLP, timing closureFront end implementation
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 8, 2026. Interested? Apply on the company site.
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