IP Post-Silicon Validation Lead
Hybrid (Vancouver)CA$187.2k - CA$280.8kFull-timePosted 1mo ago
About the role
Senior IP Validation Design Lead within AMD NBIO team, responsible for planning, validation, and debugging of hardware IP across AMD’s SOC programs, collaborating cross-functionally to ensure feature alignment and drive innovations in validation tooling and methodology.
Responsibilities
- Comprehend the SOC as a complete system including HW (Silicon), FW, BIOS & SW and ensure alignment for features, performance, and power
- Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to meet product requirements
- Defining, documenting, executing and reporting the overall functional test plan and end to end validation strategy for a set of AMD IP’s
- Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, methodology enhancement, and cross-functional initiatives
- Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of SOC programs
- Engaging in pre-silicon ‘shift left’ activities with Design Verification, Diagnostics, Emulation and other modeling frameworks to ensure readiness for first silicon and enablement of IP functionality
- Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives
- Developing knowledge of system architecture/debug and other internal IPs; supporting customer platform issues as required by customer engineering teams
Qualifications
- Bachelor’s or Master’s degree majoring in EE, CS or related field
- Outstanding foundation in Systems & SoC architecture with expertise in CPU or GPU, Memory sub-system, Fabrics, High Speed I/O subsystems, Clocks, Resets, Virtualization and Security
- Experience in digital logic design/verification/post-silicon validation
- Extensive experience with ASIC debug techniques and methodologies
- Knowledge of physical and protocol levels of common high-speed interfaces is a plus
- Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
- Strong scripting skills (e.g., Ruby, Python)
- Extensive experience with lab equipment (protocol/logic analyzers, oscilloscopes)
- Excellent communication, management, and presentation skills
- Adept at collaboration across geographies and mentoring capabilities
- Must be a self-starter and able to independently drive tasks to completion
Skills
Required:System/SoC architectureDigital logic design/verificationASIC debug techniquesScripting (Python/Ruby)
Nice to have:Lab equipment operation
Benefits
- AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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