Sr. Staff Design Verification Engineer
San Jose, CA$200k - $300kFull-timePosted 1mo ago
About the role
Senior design verification engineer focusing on RTL/ASIC/SoC development for AMD’s FPGA Product and Platform group, supporting IP development for silicon implementation and first-time-right software solutions across multi-disciplinary teams.
Responsibilities
- Participate in all stages of the design flow, from RTL development through GDS implementation.
- Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
- Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
- Collaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
- Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.
- Partner with cross-functional teams across multiple engineering disciplines and geographic locations.
- Communicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.
Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Skills
Required:RTL designSystemVerilogVerilogScriptingCollaboration
Nice to have:UVMDFT/TestingPhysical designHigh-speed interfaces/IPs
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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