SOC Design verification engineer
HyderabadFull-timePosted 1mo ago
About the role
Role focuses on planning, building, and executing pre-silicon verification for full chip, blocks, multi-chip and system-level verification to ensure a bug-free final design in AMD’s advanced workloads.
Responsibilities
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Qualifications
- Proficient in ASIC design verification with 8+ Years of experience
- Must have excellent knowledge of ASIC Design Flow and SOC architecture
- Excellent debugging skills in functional simulations
- Proficient in developing and using UVM testbenches, flows and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, C++ and SystemC
- Automating workflows in a distributed compute environment
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Scripting language experience: Perl, Python, Makefile, shell preferred
- Exposure to leadership or mentorship is an asset
- Experience in hardware security features verification or SoC level boot flow is good to have
Skills
Required:ASIC design verificationUVMVerilog/SystemVerilogC/C++Linux/Windows
Nice to have:SystemCscripting (Perl, Python, Makefile, shell)
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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