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Senior Staff Front End Automation Engineer

AMD· Engineering
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Hybrid (Penang, Malaysia)Full-timePosted 1mo ago

About the role

Senior Front-End Design Automation Engineer focusing on front-end EDA flows (lint/design-quality, static timing analysis, constraints, RTL quality signoff) with a strong emphasis on AI-based modernization and automation for faster, smarter front-end verification and signoff.

Responsibilities

  • Help shape the technical direction and roadmap for the front-end flows (lint/design-quality, STA and constraints, RTL quality signoff), including architecture, enablement, and release strategy.
  • Drive AI-based modernization — applying ML and agentic automation to lint triage, timing/constraint debug, and regression analysis.
  • Serve as a technical resource and mentor for FE flow issues, ruleset decisions, and methodology questions from design teams.
  • Drive user enablement and adoption — low-power (UPF) and timing-flow enablement, best-practice guidance, and documentation.
  • Partner with design, CAD, IP, and library teams, and maintain regression/CI (e.g., nightly pipelines) for flow quality.

Qualifications

  • Extensive experience in silicon design automation / front-end methodology / RTL flow development, with a track record of driving technical initiatives.
  • Deep expertise in front-end flows: RTL lint/design-quality, static timing analysis and constraint (SDC) development, RTL quality signoff including CDC, and low-power (UPF).
  • Strong understanding of the RTL-to-signoff flow and how front-end deliverables feed physical implementation.
  • Proficient scripting (Tcl, Python, Perl) and comfortable with flow infrastructure and regression/CI (e.g., Jenkins).
  • Hands-on with industry front-end EDA tools (Synopsys / Cadence — STA, lint, CDC).
  • Strong communication and cross-functional collaboration across distributed teams.
  • Experience applying AI/ML or LLM-based agents to EDA flows or design automation.
  • FPGA / ASIC / SoC experience in advanced nodes; familiarity with Perforce/ICManage and central IP/library releases.

Skills

Required:RTL lint/design-qualityStatic Timing Analysis (STA)RTL quality signoff (CDC/RDC)Low-power (UPF)Scripting (Tcl, Python, Perl)CI/Regression toolingEDA tools (Synopsys/Cadence)

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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