Functional Verification Lead (Memory Subsystem)
HyderabadFull-timePosted 1mo ago
About the role
SMTS Engineer to provide technical leadership and contribution on high speed Memory Controller IP Verification for DDR5/6 and UCIe designs, with focus on verification strategy, leadership, and delivery to programs.
Responsibilities
- Provide technical leadership and contribute on high speed Memory Controller IP Verification.
- Design, develop, and use simulation and/or formal based verification environments, at block and Sun-System level, to prove functional correctness of DDR5/6 RLD3 Memory Controller, UCIe IP designs.
- Drive strategies and successful verification execution on high performance IPs and/or SOC designs.
- Plan, execute, track verification activities, ensure verification closure, and deliver to programs.
- Influence Memory Controller design teams to improve overall product quality.
- Hands-on verification of memory controllers (HBM, DDR, LPDDR) and related protocols; calibrate boards for skew and jitter modeling.
Qualifications
- BS w/ 12+ yrs or MS w/ 11+ yrs or PhD w/ 9+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
- Experience with development of UVM/OVM and/or Verilog, SystemVerilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
- Proven track record on driving strategies and successful verification execution on Memory Controllers high performance IPs and/or SOC designs.
- Proven track record in technical leadership of teams of 9+ engineers (planning, execution, tracking, verification closure, and delivery).
- Hands on experience with verification of memory controllers (HBM, DDR, LPDDR); strong understanding of memory controller protocols, calibration specifications, board skew and jitter modeling.
- Strong understanding of verification techniques, including assertion and metric-driven verification; experience as a verification architect is a plus.
- Familiarity with verification management tools and database management for regression management.
- Experience with formal property checking tools (Cadence, Jasper, Synopsys) is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
- Prior silicon debug experience at tester and board level is a plus.
Skills
Required:Memory controller verificationUVM/OVMVerilog / SystemVerilogSimulation tools (VCS, IES)Memory protocols (HBM, DDR, LPDDR, UCIe)
Nice to have:Verification architecture
Benefits
- AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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