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Lead IP Verification Engineer

AMD· Engineering
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MARKHAMCA$155.2k - CA$232.8kFull-timePosted 1mo ago

About the role

Lead Verification Engineer in the AECG Group focusing on front-end design/integration for FPGA/ASIC verification, collaborating with architecture, IP design, PD, and product engineering to achieve first pass silicon success.

Responsibilities

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
  • Build the directed and random verification tests
  • Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

Qualifications

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Skills

Required:IP level ASIC verificationVerilogSystemVerilogUVMScripting (Python/Perl)
Nice to have:C/Cpp

Benefits

  • Benefits offered are described: AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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