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Verification Engineer

AMD· Engineering
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MARKHAMCA$128k - CA$192kFull-timePosted 1mo ago

About the role

Verification Engineer role at AMD focused on leading and contributing to verification of Network on Chip (NoC) IPs, subsystems, and SoCs using SystemVerilog/UVM, with a blend of simulation and formal verification methods.

Responsibilities

  • Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
  • Interact with architects and design engineers to create a comprehensive verification test plan
  • Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Identify and write coverage measures for stimulus quality improvements
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

Qualifications

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Skills

Required:SystemVerilogUVMConstraint-randomCoverage-driven verificationDebuggingCollaboration
Nice to have:Formal verificationSystemVerilog Assertions (SVA)

Benefits

  • AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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