Physical Design Lead with STA
HyderabadFull-timePosted 1mo ago
About the role
Role focused on ownership and leadership of SubSystem partitions for SoC signoff, spanning RTL to GDS execution, with emphasis on STA, EMIR, PV, and collaboration across PnR, CAD, and methodology teams to achieve first-pass silicon success.
Responsibilities
- Owns SS Partitions PnR execution and closure
- Drive new improvement in closure
- Analysis of data and feedback to Design team
- Work with PnR team members for closure convergence starting from Synthesis to Route
- Closure signoff on STA, EMIR, PV
- Work and collaborate with different business units, CAD and central methodology team to drive the requirement
- Automation to refine and improve design signoff requirement and dashboarding
- Ability to organize and present complex technical information in a crisp and concise manner.
- Interact with other PPA (equivalent) teams internal to AMD
- Identify best practices across AMD and industry to update and improve flow/project settings
- To increase the competitiveness of each stage in AMD design flow
- Ability to work with multi-level functional teams across various geographies.
- Highly organized, strong affinity for automation and prioritization.
Qualifications
- 8+ year or more experience design signoff closure
- Strong PnR backround with critical problem solving ability on improving PPA and debug
- Technical depth in CTS, Route, STA.
- EMIR driven power grid knowledge
- PnR and STA signoff correlation drive and convergence
- Strong at SDC coding and debug skills
- Drive new requirements and methodology to aid timing closure at SoC
- Identify the gaps and support flows
- Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
- Drive team towards common requirements and flows
- Experienced in deploying and implementing ML techniques and algorithms in physical design.
- Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
- Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
- AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.
Skills
Required:PnR (Place and Route)STAEMIRSDC codingScripting languages
Nice to have:CTSML techniques in physical design
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 8, 2026. Interested? Apply on the company site.
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