SDC, Synthesis and STA Engineer
Hyderabad, IndiaFull-timePosted 1mo ago
About the role
Role focused on planning and executing front end implementation of IPs, ownership of SDC development and timing closure, with potential expansion to synthesis, LEC, CLP, prelayout/postlayout STA, and collaboration with design and PNR teams.
Responsibilities
- Own constraints, SDC development for IPs, SS and SoCs, including generation, verification, promotion, demotion and equivalence using third-party or in-house tools
- Front end implementation responsibilities may include synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
- Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
- Collaborate with designer and PNR teams to achieve closure
- Understand duration required, plan and execute as per schedule
- Complete quality delivery for synthesis and timing closure
- Debug and resolve technical issues
Qualifications
- Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering
Skills
Required:SDC developmentConstraints developmentDebugging
Nice to have:SynthesisPrelayout STA / Postlayout STALint/CDC/RTL & Netlist static checksDFT conceptsAutomation / Scripting interest
Benefits
- AMD benefits at a glance (link provided)
Last updated Sep 24, 2026. Interested? Apply on the company site.
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