Full Chip Timing Lead
HyderabadFull-timePosted 1mo ago
About the role
Full Chip Timing Lead - PD role focused on SoC Full Chip timing closure and optimization, including high frequency CPU, HBM, DDR, and Serdes interfaces. Responsible for SDC validation, timing signoff, and collaboration with methodology and CAD teams to achieve first-pass silicon success.
Responsibilities
- Owns Full chip Timing Closure
- Clock build guidance using multiple methods MSCTS, Mesh
- Design repeater feedback based on timing across blocks
- Drive new improvement in closure
- Analysis of data and feedback to PD execution team
- SDC analysis and feedback
- Work with PnR engineer for timing convergence
- Drive the common STA methodology in the business unit
- Work and collaborate with different business units, CAD and central methodology team to drive the requirement
- Automation to refine and improve design signoff requirement and dashboarding
- Ability to organize and present complex technical information in a crisp and concise manner
- Interact with other PPA (equivalent) teams internal to AMD
- Identify best practices across AMD and industry to update and improve flow/project settings
- To increase the competitiveness of each stage in AMD design flow
- Ability to work with multi-level functional teams across various geographies
- Highly organized, strong affinity for automation and prioritization
Qualifications
- 8+ year or more experience design signoff closure
- Timing closure experience at SoC and block level
- Technical depth in STA, High freq interface closure in hierarchical STA
- Multi voltage closure
- Timing ECO flow
- Hyperscale, Yield analysis
- PnR and STA signoff correlation drive and convergence
- Strong at SDC coding and debug skills
- Drive new requirements and methodology to aid timing closure at SoC
- Identify the gaps and support flows
- Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile
- Drive team towards common requirements and flows
- Experienced in deploying and implementing ML techniques and algorithms in physical design
- Low power physical design implementation flows from RTL to physical verification
- Experience with tools from Synopsys, Cadence and Mentor
- AMD block TileBuilder and lower tech nodes (5/3/2) is a plus
Skills
Required:STA timing closureSDC coding and debuggingScriptingP&P/Signoff processesCommunication
Nice to have:Automation
Benefits
- Benefits offered are described: AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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