Senior Physical Design Engineer
Hybrid (Markham)CA$105.6k - CA$158.4kFull-timePosted 1mo ago
About the role
Senior-level physical design engineer role focused on end-to-end physical implementation for high-speed IPs and SoCs, including synthesis, floorplanning, placement, clocking architectures, routing, and timing closure for >2 GHz designs across PCIe, SATA, Ethernet, and Infinity Fabric interfaces. Located in Markham, Canada with opportunity to contribute to next-generation AMD microprocessors, GPUs, and related systems.
Responsibilities
- Looking for an experienced Design Engineer who will focus on all physical implementation aspects of next generation IPs. This team deals with multiple I/O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer.
- This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA closure.
- The team will work on cutting edge IP for these I/O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and support SoCs worldwide.
Qualifications
- B.E. or M.E in Electrical or Computer Engineering (or equivalent)
- Industry experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs
- CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python
Skills
Required:SynthesisFloorplanningPlacementClock Tree SynthesisPost Route Timing Closure
Nice to have:DFTCDC/PTPX/STA/LINTScripting (TCL, Python)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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