SerDes RTL Design Engineer
Hybrid (San Jose, CA / US)$166.4kFull-timePosted 1mo ago
About the role
RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes for AMD SerDes Technology team.
Responsibilities
- Collaborate with system link architects to micro-architect cutting edge high-speed SerDes PHY design
- RTL design of digital blocks, such as calibration and adaptation loops, digital signal processing, clock-data-recovery
- Apply low power design techniques and perform PPA analysis
- Verify intended functionality with block-level test bench
- Run design checker tools such as LINT/CDC/RDC etc.
- Behavioral modeling of custom circuit using Verilog/System Verilog
- Support functional verification and debug of design, and static timing closure
- Collaborate with physical design and validation teams to perform pre-tape out design sign-off and silicon bring-up
Qualifications
- Bachelor's or master’s degree in electrical engineering, computer engineering, or related field
Skills
Required:Verilog/System VerilogDigital designDesign verification tools
Nice to have:Synthesis flow and static timing analysisLow power designClock-domain crossing/multi-clock domain designProgramming/scriptingSerDes PHY / high-speed I/O
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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