Sr. Design Verification Engineer
Hybrid (Santa Clara, CA or Austin, TX)$141.8k - $212.6kFull-timePosted 1mo ago
About the role
Senior-level design verification engineer for AMD's Network Technologies Solutions Group focusing on IP/subsystem/SoC verification for high-performance networking data-paths, with UVM/SystemVerilog expertise, debugging, and cross-functional leadership.
Responsibilities
- Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
- Drive test plan creation, feature mapping, and coverage strategy for complex networking and data‑path IP.
- Develop high‑quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
- Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
- Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
- Optimize simulations, coverage closure, and verification sign‑off methodology.
- Use industry‑standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
- Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).
- Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high‑quality deliverables.
- Participate in design reviews, micro‑architecture definition, and bring a verification perspective into early design stages.
- Mentor junior engineers and provide technical leadership within the verification team.
Qualifications
- Expert‑level knowledge of SystemVerilog and UVM
- Strong hands‑on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
- Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies
- Strong debug skills across architecture, RTL, and testbench layers
- Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑path components
- Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure
Skills
Required:SystemVerilog
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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