CPU Core Staff DFT Engineer
Hybrid (Santa Clara, CA)$200k - $300kFull-timePosted 1mo ago
About the role
Senior DFT/ATPG engineer responsible for ATPG/DFT for next-generation AMD high-performance CPU cores, collaborating with architecture, IP design, Physical Design, and Product Engineering to achieve first-pass silicon success.
Responsibilities
- Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
- Debug of low coverage, DRC violation fixes and coming up with efficient and effective solutions for these issues
- Proficient in logic design using Verilog
- Debugging complex test pattern issues and simulation failures
- Support of Silicon bring up activities
- Participating in post-silicon debug
- Comfortable in Linux environment and writing/using scripting languages such as Perl, TCL, etc.
- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
- Excellent presentation and inter-communication skills
- Bachelor's in Electrical Engineering/Computer Engineering
Qualifications
- Bachelor's in Electrical Engineering/Computer Engineering
Skills
Required:DFTATPGScan compressionVerilogLinuxScripting (Perl, TCL)
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 8, 2026. Interested? Apply on the company site.
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