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RFIC Layout Engineer

Apple· Hardware
Apply on company site
Hybrid (San Diego, CA), Hybrid (Irvine, CA), Hybrid (Sunnyvale, CA)$118k - $207.1kFull-timePosted 1mo ago

About the role

RFIC Layout Engineer role within Apple’s wireless SOC organization, focusing on detailed transistor-level RF/analog layout, integration, and top-level verification to deliver energy-efficient wireless silicon and cutting-edge technology.

Responsibilities

  • Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.
  • Co-work with designers on block-level and top-level floorplanning.
  • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
  • Top-level layout integration and verification, schedule management.
  • Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.

Qualifications

  • Minimum requirement of a bachelors degree
  • Understanding of RC delay, electromigration, and coupling.
  • Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems.
  • Good communication skills and ability to work with multi-functional teams.
  • Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience).
  • Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing.
  • Good understanding of RC delay, electromigration, and coupling.
  • Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology.
  • Capability to lead other layout engineers for top-level integration.
  • Scripting skills in PERL or SKILL are a plus.
  • Extensive knowledge of CADENCE layout tools.

Skills

Required:Bachelor’s degreeRF/analog layout experience in deep sub-micron CMOS (16nm and lower, FinFET)Device matching, parasitics minimization, RF shielding, high-frequency routingRC delay, electromigration, couplingCALIBRE DRC/ERC/LVS (FinFET)CADENCE layout tools
Nice to have:Leadership of layout engineersScripting (PERL or SKILL)

Benefits

  • Comprehensive medical and dental coverage
  • retirement benefits
  • discounted products and free services
  • reimbursement for certain educational expenses including tuition
  • discretionary bonuses or commission payments as well as relocation eligibility
  • Apple shareholder opportunities through stock programs
  • employee stock purchase plan
Last updated Sep 18, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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