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Senior Serdes Characterization & Post-Silicon Validation Engineer

K2 Space· Silicon
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Seattle, WAFull-timePosted 4w ago

About the role

Hands-on senior engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs, collaborating across SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams; responsible for building high-speed test and validation capability from the ground up and supporting transition from chip-level characterization to product integration.

Responsibilities

  • Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces.
  • Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions.
  • Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin.
  • Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior.
  • Perform BER and stress testing across representative and worst-case channels.
  • Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.
  • Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.
  • Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system-level link bring-up.
  • Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting.
  • Support the transition from chip-level SerDes characterization to product integration and system-level validation.
  • Contribute to building the high-speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up.

Qualifications

  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
  • Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
  • Deep hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
  • Experience with eye diagrams, jitter decomposition, bathtub curves, BER testing, stressed-eye testing, and receiver sensitivity characterization.
  • Strong understanding of package/PCB channels, insertion/return loss, crosstalk, reflections, and channel de-embedding.
  • Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces.
  • Strong debugging skills across silicon, package, PCB, firmware, and system boundaries.
  • Ability to work closely with SerDes IP/design, SI, package, board, firmware, and digital teams.
Last updated Sep 23, 2026. Interested? Apply on the company site.

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