Staff/Principal Functional Verification Engineer (Memory Subsystem)
HyderabadFull-timePosted 4w ago
About the role
SMTS Engineer to provide technical leadership and contribution on high speed interface Verification for memory controller IPs and SOC designs, with focus on UCIe, DDR5/6, and related memory interfaces. Requires hands-on verification experience, leadership of teams, and ability to influence Memory Controller design programs.
Responsibilities
- Provide technical leadership and contribution on high speed interface verification.
- Design, develop and use simulation and/or formal based verification environments, at block and Sun-System level, to prove the functional correctness of UCIe, DDR5/6 RLD3 Memory Controller IPs/ Designs.
- Plan, execute, track, and deliver verification closures to programs.
- Influence Memory Controller design teams to improve product quality.
- Utilize UVM/OVM, Verilog/SystemVerilog testbenches and simulation/debug tools (e.g., Synopsys VCS, Cadence IES).
- Perform silicon debug at tester/board level (plus).
- Apply verification techniques including assertion and metric-driven verification; consider formal property checking tools.
Qualifications
- BS with 12+ yrs, MS with 11+ yrs, or PhD with 9+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
- Experience with development of UVM/OVM and/or Verilog, SystemVerilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
- Proven track record in driving strategies and successful verification execution on memory controllers high performance IPs/SOC designs.
- Proven technical leadership of teams (9+ engineers) including planning, execution, tracking, verification closure, and program delivery.
- Hands-on experience with verification of high speed interfaces such as UCIe (a plus).
- Strong understanding of verification techniques, including assertion and metric-driven verification; experience as a verification architect (a plus).
- Familiarity with verification management tools and database management for regression management.
- Experience with formal property checking tools (Cadence, Jasper, Synopsys) (a plus).
- Experience with gate level simulation, power verification, reset verification, contention checking (a plus).
- Prior silicon debug experience at tester and board level (a plus).
Skills
Required:UVM/OVMVerilog/SystemVerilogSimulation tools (VCS, IES)Memory controller protocolsLeadership/people management
Nice to have:Formal verification
Benefits
- AMD benefits at a glance (link provided)
Last updated Sep 24, 2026. Interested? Apply on the company site.
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