CPU Microarchitecture & Cache RTL Design Engineer
Fort Collins, CO$144.8k - $217.2kFull-timePosted 4w ago
About the role
Senior VLSI RTL Design Engineer focusing on high-performance, energy-efficient cache and fabric solutions for AMD’s next-generation cores and caches. Based in Fort Collins, CO.
Responsibilities
- Collaborate with Cache and CPU Architects to design, document, and execute optimized high-performance Cache and Routing Fabric designs.
- Collaborate with Physical Design teams to develop RTL optimized for physical implementation and timing closure.
- Collaborate with Design Verification teams to develop architectures and features that are clearly documented and verifiable.
- Collaborate with Design for Test teams to develop RTL that is reliable, testable, and manufacturable.
- Work across global teams to solve complex architectural interactions between IP and SoC designs.
- Develop improvements to CPU designs by increasing quality, simplifying design complexity through innovation, and strengthening technical collaboration across teams.
- Solve complex design and tool challenges through innovative and practical solutions while contributing to technical excellence across the organization. Create technical presentations for peers and management.
- Guide and mentor other engineers.
Qualifications
- Bachelor’s or master’s degree in computer engineering, Electrical Engineering, or a related technical field.
Skills
Required:Cache architecture development and executionCPU Coherency, Coherent NoC, Cache Allocation and Replacement Policy, Quality of Service, Fairness, Forward ProgressDigital RTL Design, Verilog HDL, and scriptingCross-functional collaboration
Nice to have:Mentoring
Last updated Oct 22, 2026. Interested? Apply on the company site.
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