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PD Leadership role

AMD· Engineering
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Hybrid (Bangalore)Full-timePosted 4w ago

About the role

Lead Physical Design (PD) Architect for RTL2GDSII execution, driving timing closure, power optimization and signoff strategies across multiple SOC/ASICs. Role involves mentoring, cross-functional leadership, methodology development, and engagement with industry forums to advance RTL2GDSII flows.

Responsibilities

  • Go to person for multiple SOC/ASICs in RTL2GDSII domain comprising of physical design implementation, timing closure and various signoff (timing, physical verification, IREM, Power etc) activities
  • Provide leadership and mentoring towards convergence of highly complex tiles/partitions/blocks spanning across multiple Subsystems and IPs , not limited to PCIE, DDR, CPUs, GPUs, Gfx, ETH, UCIE etc.
  • Cross-Functional Leadership - Collaborate with various teams, including architecture, design, verification, DFT and product management, to ensure PPA goals are met.
  • Strategic Planning: Provide strategic direction to SOC/Subsystem and Tile/Partition level execution, that align with industry trends and company goals.
  • Foster a culture of innovation by encouraging research and experimentation in RTL2GDSII activities. Identify opportunities for patents and publications.
  • Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks with expert level understanding of timing convergence (both tile-level and full chip timing), and full chip integration flows.
  • Understanding of design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle.
  • Drive methodology development ideas and drive internal forums towards adoption of latest flow/methodologies and AI technologies.
  • Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology.
  • Provide technical direction, guidance, mentorship and support to the engineering team.
  • Stay abreast of the latest advancements in RTL2GDSII and represent the company in industry forums, conferences, and collaborations to influence and adopt best practices.
  • Define and track key performance indicators (KPIs) related RTL2GDSII . Report on progress and impact to senior leadership and executives.
  • Possess good understanding of foundry DRM and must have collaborated with DTCO and FTO in the past

Qualifications

  • B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.

Skills

Required:Physical Design leadershipSynthesisConstraintsPlacement and Routing (P&R)Timing SignoffPhysical VerificationIP IntegrationScriptingEDA ToolsPower, Performance and Area (PPA) optimizationCommunication & Leadership

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 8, 2026. Interested? Apply on the company site.
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