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CPU Architecture and RTL Design Engineer

AMD· Engineering
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Hybrid (Dublin or Cork)Full-timePosted 4w ago

About the role

AMD is seeking a CPL CPU Architect/RTL Design Engineer to drive the definition, implementation (RTL design), and integration of Clocking, Reset and Power in next-generation CPUs and caches. Collaboration across logic, physical design, and verification teams to deliver high-performance, power-efficient CPU designs.

Responsibilities

  • Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs.
  • Reliably deliver a design from concept through tapeout by innovating through complex and challenging requirements.
  • Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis.
  • Identify customer challenges and insert a compelling AMD value proposition to address challenges.
  • Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs.

Qualifications

  • Proficiency with Verilog HDL, Clock/Power Domain Crossing concepts, and Power Management concepts.
  • Understanding of modern CPU architecture - prior experience designing shared cache or last level cache and related IPs a plus.
  • Eagerness to learn and grow as a CPL design engineer.
  • Collaborate effectively towards the success of the project by working closely with logic design, physical design and verification teammates across the wider organization.
  • Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas to facilitate design delivery.

Skills

Required:Verilog HDLClock/Power Domain CrossingPower Management
Nice to have:CPU Architecture

Benefits

  • Benefits offered are described: AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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