DFT Timing Lead
Hybrid (Bangalore)Full-timePosted 4w ago
About the role
Senior/Staff/Manufacturing Test Senior (SMTS) or Manufacturing Test Specialist (MTS) role in the S3 SoC DFT Team, focusing on structural DFT, ATPG, and MBIST to ensure quality of next-generation AMD SoCs. Collaboration with design and physical teams, development of DFT constraints, and automation scripting.
Responsibilities
- Develop full chip DFT Synthesis and DFT STA constraints.
- STA constraint development of DFT modes (ScanShift, Atspeed, MBIST)
- Set up DFT timing constraints, defining the overall SOC Test STA methodology.
- Working with the Design team to clean-up all the DFT related constraint issues
- Closely work with physical design team to generate and validate timing constraints
- Developing, improving and maintaining automation scripts as necessary
Qualifications
- B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8 to 15 years of DFT Experience
Skills
Required:DFT architectureStatic timing analysis (STA)DFT constraints handlingSOC timing closure in DFT modesRTL quality check tools (Spyglass, CDC, Lint)debug and scripting
Last updated Oct 22, 2026. Interested? Apply on the company site.
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