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NPU Compiler Engineer

AMD· Engineering
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San Jose, CA$172kFull-timePosted 4w ago

About the role

Software engineer role focused on improving performance of AI workloads on NPUs within AMD's ML accelerator stack, contributing to next-generation compiler tools for Vitis-AI and Ryzen-AI platforms.

Responsibilities

  • Enhance, implement and design and implement compiler passes in MLIR framework for implementing and optimizing AI workloads on NPU.
  • Analyze and debug functional and performance issues.
  • Build infrastructure for analysis and debug of regression suites
  • Apply AI and coding agents to compiler development, debugging, test generation, and performance analysis.
  • Apply a data minded approach to target optimization efforts
  • Debugging/fix existing issues and research alternative, more efficient ways to accomplish the same work
  • Develop technical relationships with peers and partners

Qualifications

  • Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
  • Strong object-oriented programming background, C/C++ preferred
  • Deep hands-on experience with MLIR optimization and lowering passes
  • Strong knowledge of compiler architecture, intermediate representations, transformation passes, and optimization pipelines.
  • Strong understanding of NPU architecture, including parallel execution, memory hierarchy, caches, registers, synchronization, and occupancy.
  • Strong C++ and python skill
  • Experience with AI compilers, tensor or graph compilers, machine learning frameworks
  • Experience with debugging using SystemC and RTL simulators

Skills

Required:Object-oriented programmingMLIR optimization and lowering passesCompiler architecture and IRsNPU architecture understandingC++Python
Nice to have:AI/ML frameworksSystemC and RTL debugging

Benefits

  • Benefits offered are described: AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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