RTL Design Engineer – Power Design
Hybrid (Austin, TX)$200k - $300kFull-timePosted 4w ago
About the role
RTL Power Design Specialist to join the Security IP (SECIP) design team at AMD. Responsible for defining IP-level power specifications, driving power targets, and developing advanced power design and measurement methodologies to enable aggressive power targets across SoC designs.
Responsibilities
- Develop and maintain RTL-level IP power specifications, and align IP power architecture and solutions with SoC power requirements in partnership with SoC, IP functional design, and power design teams.
- Define, track, and drive IP power targets by correlating power design intent with measurement results and identifying optimization opportunities.
- Collaborate with verification teams to develop power vectors for simulation-based power measurements.
- Partner with static power measurement teams to develop and maintain power regression infrastructure, monitor power health metrics, debug power-related issues, and analyze results to drive design improvements.
- Work with corporate power methodology and SoC power teams to adopt advanced power architecture, design, analysis, and measurement methodologies to meet the SoC power requirements.
- Contribute to corporate power methodology development and, as an advanced team member, influence the SoC power team's IP-level power strategy.
- Provide technical leadership in power architecture, design, analysis, and measurement methodology development, while mentoring team members and promoting best practices across projects.
Qualifications
- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or closely related field.
- Proficiency in Verilog/SystemVerilog and scripting languages such as Python, Tcl, Perl, and Ruby, as well as Makefile-based development environments.
- Deep knowledge of modern RTL-level power architecture, design, analysis, measurement methodologies, and industry best practices.
- Strong understanding of microprocessor (MP) subsystem architectures, RTL microarchitectures for datapath accelerators, and low-power design methodologies.
- Solid understanding of industry-standard on-chip bus and interface protocols, including AMBA, AXI, and AHB.
- Experience with ASIC design and verification tools, including RTL simulation, linting, synthesis, power-aware verification, debugging, and related design flows.
- Demonstrated ability to collaborate effectively across IP, SoC, methodology, and verification teams to drive technical solutions and achieve project goals.
Skills
Required:Verilog/SystemVerilogPythonTclRTL power designAMBA/AXI/AHB
Benefits
- Benefits described in AMD benefits at a glance (link provided in posting)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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