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Lead Design Verification Engineer-Memory Controller

AMD· Engineering
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San Jose, CA$200k - $300kFull-timePosted 4w ago

About the role

Senior Staff Silicon Design Verification Engineer role within AMD's Adaptive and Embedded Computing Group (AECG), focusing on verification of high-speed memory controller IPs (DDR5, LPDDR6, HBM4), NoC, and cryptography, at IP and SoC levels with leadership responsibilities.

Responsibilities

  • Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (DDR5, LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.
  • Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.
  • Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.
  • Develop and execute comprehensive verification plans, including testbenches and test cases.
  • Collaborate with design, architecture, and software teams to define and implement verification strategies.
  • Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.
  • Mentor and guide junior engineers, fostering a collaborative and innovative team environment.

Qualifications

  • BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering, or Computer Science.

Skills

Required:Verification leadershipUVM and SystemVerilogMemory controller protocols and calibration
Nice to have:Formal verificationTest bench automationSilicon debugging
Last updated Sep 24, 2026. Interested? Apply on the company site.
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