Principal Memory Sub-System Validation Lead
Santa Clara, CA$229.6k - $344.4kFull-timePosted 4w ago
About the role
Lead for pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM) for AMD’s Datacenter GPU (Machine Instinct). Interfaces with DRAM architecture, Memory Controller Design, DV, DDR PHY, DRAM product engineering, and software teams to ensure memory technologies are delivered from architecture to production.
Responsibilities
- All aspects of pre- and post-silicon validation from planning, execution and debug.
- Develop and execute test plans for HBM Functional and Electrical Validation (PVT Shmoo Characterization).
- Lead by example, mentor junior engineers, and collaborate with cross-functional teams to debug and resolve issues.
- Be hands-on with lab tools and comfortable working in a lab environment.
Qualifications
- Bachelors or Masters in Electrical or Computer Engineering
- Experience leading complex test plans independently
- Extensive knowledge of high bandwidth memory subsystem, SoC memory architecture, Unified Memory controller, PHY design and high speed IO interface, DRAM device, and calibration/training mechanisms
- Strong debugging skills and ability to drive resolution of critical problems under pressure
- Ability to summarize complex technical details for executive reporting
- Experience with DDR, LPDDR, HBM SoC validation, verification and debug (preferred)
- Hands-on experience with JTAG, I2C, testers and lab tools (preferred)
- Strong programming skills (C/C++, Python) and comfort with Linux or Windows (preferred)
- Experience developing test cases for ML and HPC applications (preferred)
- Ability to work in a dynamic, multi-project environment
- Team-oriented and collaborative mindset
Skills
Required:Memory subsystem validationDebugging and root-cause analysisLeadership and mentorship
Nice to have:Programming
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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