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Senior Manager - Analog Design

AMD· Engineering
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Santa Clara, CA$232k - $348kFull-timePosted 4w ago

About the role

Senior managerial role leading the Memory I/O design team responsible for LPDDR IP architecture, specification, modeling, and high-speed analog/digital block design. Focus on circuit architecture, calibration/equalization algorithms, and link performance modeling for future LPDDR PHY implementations.

Responsibilities

  • Manage and contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHYs
  • Work closely with Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
  • Manage execution and deliverables across customers and stakeholders
  • Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design
  • Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits
  • Participate and contribute to the definition of development flows that improve efficiency and quality of execution

Qualifications

  • Bachelors,Masters or Ph.D. degree in computer engineering/Electrical Engineering

Skills

Required:Circuit architecture and design of LPDDR PHYsAnalog Mixed Signal collaborationModeling for link-level performanceDocumentation and training leadership
Nice to have:Development flows optimization
Last updated Oct 15, 2026. Interested? Apply on the company site.
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