Senior Functional Verification Engineer (Memory Subsystem)
HyderabadFull-timePosted 4w ago
About the role
MTS Engineer to provide technical leadership and contribution on high speed interface Verification for memory subsystem designs (UCIe, DDR5/6). Responsible for designing, developing, and using verification environments (block and Sun-System level) to prove functional correctness of memory controller IPs and SOC designs, with leadership responsibilities including planning, execution, and delivery.
Responsibilities
- Provide technical leadership and contribution on high speed interface verification.
- Design, develop and use simulation and/or formal based verification environments (block and Sun-System level).
- Prove functional correctness of UCIe, DDR5/6 memory controller designs.
- Drive verification strategies and successful verification execution for high performance IPs and/or SOC designs.
- Lead and influence Memory Controller design teams to improve product quality.
- Plan, execute, track verification activities, ensure closure and delivery to programs.
Qualifications
- BS with 8+ years or MS with 7+ years or PhD with 7+ years in Electrical Engineering, Computer Engineering or Computer Science.
- Experience with development of UVM/OVM and/or Verilog, SystemVerilog test benches and usage of simulation tools/debug environments (e.g., Synopsys VCS, Cadence IES) to verify memory controller IPs.
- Proven track record in verification leadership and delivering on memory controllers high performance IPs and/or SOC designs.
- Experience leading teams of 9+ engineers including planning, execution, verification closure, and program delivery.
- Hands-on experience with verification of high speed interfaces like UCIe is a plus.
- Strong understanding of verification techniques, including assertion and metric-driven verification; experience as a verification architect is a plus.
- Familiarity with verification management tools and regression database management.
- Experience with formal property checking tools (Cadence, Jasper, Synopsys) is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
- Prior silicon debug experience at tester and board level is a plus.
Skills
Required:High speed interface verificationUVM/OVMVerilog/SystemVerilogSimulation tools (VCS, Cadence IES)Verification leadership
Nice to have:Formal verification
Benefits
- AMD benefits at a glance (link)
Last updated Oct 8, 2026. Interested? Apply on the company site.
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